In recent years, with the decrease in size and enhancement in performance of electronic apparatuses and the increase in variety and the decrease in price of products, a decrease in cost of multilayer circuit boards with a high density, or a simplification of part mounting technologies and manufacturing technologies has been required for printed circuit boards mounted thereon.
The build-up multilayer printed circuit board made by International Business Machines (IBM) Corporation was suggested as a multilayer circuit board with a high density.
The build-up multilayer printed circuit board has a configuration such that a build-up layer capable of being finely wired is stacked one by one on a core substrate and has been used in various electronic apparatuses, since it can be wired relatively finely in comparison with conventional circuit boards.
As the decrease in size and the enhancement in performance of electronic apparatuses and the increase in variety of products further advances, a variety of requirements such as an increase in the number of build-up layers, an introduction of a stacked via structure, a decrease in diameter of a through-hole formed in a core substrate, a decrease in pitch between the through-holes, and a decrease in board thickness have been desired to the build-up multilayer circuit board.
However, in the build-up multilayer circuit board, the processes required to realize the increase in the number of build-up layers, the stacked via structure, and the like, are complicated and thus the manufacturing cost thereof increases, thereby increasing the price thereof.
Therefore, in order to solve the above-mentioned problems, there has been suggested a multilayer printed circuit board with an all-layer IVH structure which has a high degree of freedom in wiring design, which can realize a stacked via structure, and which is suitable for high-speed signal transmission (for example, see Patent Document 1).
The multilayer circuit board is the above mentioned multilayer circuit board having a 4-layer inner via-hole structure and uses as a wiring substrate a sheet substrate member (prepreg) in which an epoxy resin as a thermosetting resin is impregnated in aramid nonwoven fabric.
The multilayer circuit board is manufactured using a via forming method for prepreg.
A through-hole is first formed in a sheet substrate member, and the through-hole is then filled with conductive paste containing metal particles and dried and hardened. Then, the conductive paste is hardened by thermally pressing a copper foil on both surfaces thereof, thereby forming a double-sided copper panel. A double-sided circuit board is formed in which circuit patterns are formed on both surfaces thereof by etching the double-sided copper panel. Next, by disposing the sheet substrate member on both surfaces of the double-sided circuit substrate, disposing a copper foil outside of the sheet substrate members, and then thermally pressing them, the 4-layer inner via-hole structure is formed.
There has also been suggested a multilayer circuit board having an all-layer IVH structure which can be multilayered by a simultaneous lamination method (for example, see Non-patent Document 1).
The multilayer circuit board is an all-layer IVH circuit board which can be obtained by the simultaneous lamination method. The multilayer circuit board can be obtained by preparing a single-sided circuit board having wiring patterns and via-holes in each layer using a single-sided rigid copper lamination panel formed of a glass cross epoxy substrate, applying an adhesive made of a thermosetting resin to the surface of the single-sided circuit board opposite to the surface having the wiring patterns formed thereon, and then simultaneously laminating a plurality of single-sided circuit boards to which the adhesive is applied.
The simultaneous lamination method has the following features. A stacked via structure or a pad-on-via structure can be easily realized, and the diameter of via lands can be decreased because the via position hardly varies at the time of the simultaneous lamination in comparison with a method of performing a via process to the prepreg. In addition, it is possible to obtain a high yield by simultaneously laminating only the boards having no defect. Furthermore, the process is very simple and the manufacturing time can be greatly reduced by manufacturing the layers in parallel to each other.
As a simultaneous lamination method, there has been suggested a method different from the above-mentioned simultaneous lamination method (for example, see Non-patent Document 2).
In the simultaneous lamination method, a plurality of copper laminated panels in which an adhesive layer using a thermosetting resin as a base and a previously prepared cover film are attached to a surface opposite to a copper surface of a single-sided copper laminated panel made of a thermosetting resin are prepared, desired circuit patterns are formed on the copper surfaces of the single-sided copper laminated panels by etching, vias are formed on the single-sided copper laminated panels out of conductive paste, the cover films are removed from the single-sided copper laminated panels, and then the single-sided copper laminated panels are simultaneously laminated.
There has been suggested a multilayer circuit board having an all-layer IVH structure which can be multilayered by a simultaneous lamination method not using an adhesive (for example, see Patent Document 2).
The multilayer circuit board includes an insulating substrate made of a thermoplastic resin containing polyaryl ketone and polyether imide. In the simultaneous lamination method, the multilayer circuit board is manufactured by setting the insulating substrate before the simultaneous lamination in an amorphous state, simultaneously laminating the insulating substrates at a temperature higher than the glass transition temperature of the thermoplastic resin so as to cause a thermal fusion between the layers, and then additionally crystallizing the layers.    [Patent Document 1] Japanese Unexamined Patent Publication No. 7-176846    [Patent Document 2] Japanese Patent No. 3514647    [Non-Patent Document 1] Akira ENOMOTO, “All Layer IVH Printed Wiring Board Using Single Step Laminating Process”, Electronics Packaging Academic Journal, Japan Institute of Electronic Packaging., November of 2000, vol. 3 (7), P544-547    [Non-Patent Literature 2] Shuji MAEDA and three others, “Simultaneous Multilayer Circuit Board Material and Corresponding Process”, MES2004 14-th Microelectronics Symposium Collected Papers, Japan Institute of Electronics Packaging., October 14 of Heisei 16, P341-344